The present invention relates to a structure, design structure and method for providing balanced/equal phase delay for on-chip transmission line circuits.
Differential signaling and I Q (in-phase and quadrature) signals used in electronic circuits and systems, such as amplifiers, modulators/mixers, receivers/transmitters etc., require an equal phase delay line pair to connect one device to another. Current solutions to ensure each transmission line has the same phase delay include laying out the line pair with the same physical length. However, for complicated on-chip circuits and systems, it is not always efficient or practical to obtain the same layout length for a line pair requiring equal/balanced phase delay. Accordingly, a solution is needed to achieve the same electrical phase delay for a line pair having unequal physical lengths in an on-chip environment.